The Fujitsu Monaka made its detailed debut at Hot Chips 2026 on August 24, giving the industry its first close look at the company’s 144-core Arm server processor. Fujitsu confirmed that the chip runs dual 256-bit SVE2 vector units, a reduction from the 512-bit SVE found in its A64FX predecessor, and that its entire last-level cache resides on a separate 5nm die positioned beneath the 2nm compute die.
Ryohei Okazaki, lead architect on Fujitsu’s processor development team, described the design as a made-in-Japan CPU engineered specifically for AI performance and power efficiency. The processor targets what Fujitsu calls green AI data centers and received support from Japan’s New Energy and Industrial Technology Development Organization. Monaka arrives in two SKUs: a 350W air-cooled version with a 2.1 GHz base clock and a 500W liquid-cooled version with a 2.9 GHz base clock. Evaluation samples are available now, with volume production scheduled for 2027.
A Three-Die Stack That Isolates the Cache
Monaka organizes its silicon into three distinct tiers. A 2nm core die built on TSMC N2P handles compute, a 5nm SRAM die on TSMC N5 holds the full last-level cache, and a separate 5nm IO die manages input and output. The core die is stacked face-to-face on top of the SRAM die using hybrid bonding, and it sits on the cooling side because it generates the most heat. The IO die connects to the SRAM die through a silicon interposer.
Fujitsu keeps 2nm silicon under 30 percent of total die area. According to Okazaki, that split allows the company to accelerate the time to market for its 2nm-based chip by shifting components that scale poorly onto the 5nm SRAM and IO dies. Placing the complete cache on its own stacked die distinguishes Monaka from AMD’s 3D V-Cache, which bonds extra SRAM atop a compute die that already carries L3. The approach lines up more closely with Intel’s Clearwater Forest, where local cache sits in a base tile with compute stacked above.
Fujitsu also relocated the low-dropout voltage regulators onto the 5nm SRAM die, since analog circuits scale poorly at 2nm. Those regulators sit directly beneath the core’s floating-point units to support per-core dynamic voltage and frequency scaling. When asked about core-to-core latency, given that the core dies sit on opposite sides of the package and route traffic through the IO die, Fujitsu pointed to the face-to-face hybrid bonding between the core and SRAM dies but declined to share specific latency figures.
Why Fujitsu Narrowed the Vector Datapath
A notable change involves the move from 512-bit SVE in A64FX to 256-bit SVE2 in Monaka. Okazaki explained that the chip is built for the data center and that Fujitsu wanted to minimize core size for the best balance of cost and performance. The narrower units also reduce SIMD width for general-purpose code.
A64FX, the 7nm CPU that powered the F
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Image: tomshardware.com
