Samsung has laid out a three-phase plan to reshape high-bandwidth memory (HBM) into an integrated memory-and-compute system, ending with an architecture called zHBM that positions the processor directly beneath the DRAM stack and removes the traditional 2.5D interposer connection between the two. Speaking at Hot Chips 2026, Sangwook Han of Samsung’s DRAM design team pointed to the base die as the central component driving this shift, a change that started when the company chose to build the HBM base die on an advanced logic process.
In standard HBM, the base die (B-die) was manufactured on the same DRAM process node as the core dies (C-dies) stacked above it. Beginning with HBM4, Samsung shifted the base die to a 4nm logic process, mainly to cut power consumption and reduce die area. That decision also delivered a far more capable piece of silicon. According to the company, a base die built on the same class of logic process as XPUs can do much more than act as a simple data interface, opening the door to offloading additional functions until the physical gap between memory and processor disappears entirely.
Why Current HBM Is Running Into Limits
Today’s HBM design stacks multiple DRAM core dies vertically on a base die, linked by thousands of TSVs. The stack sits next to an XPU on an interposer, with the base die connecting the memory and compute silicon. Bandwidth has driven each generation forward. A current HBM4 stack delivers roughly 1 to 5 TB/s of bandwidth through 1,000 to 2,000 I/Os running at about 8 to 16 Gbps each, and those numbers are set to climb with future generations.
The challenge is that conventional scaling methods are hitting walls. TSV signaling speed is hard to raise, so newer generations have added more TSVs, which eats into area and forces tighter TSV pitches. The PHY has also grown more demanding, with HBM4 doubling the data I/O count from 1,024 to 2,048 DQs as signaling speeds continue to rise. Power is the larger concern. Even though energy per bit is improving, total HBM power keeps increasing because bandwidth is scaling faster. Moving the base die to an advanced logic node, with denser and more efficient logic, is Samsung’s answer to reducing that draw. The company calls this broader direction custom HBM (cHBM), keeping the conventional DRAM stack while tailoring the logic beneath it for a specific accelerator.
Phase 1: Reclaiming Processor Area
The first stage focuses on returning silicon area to compute, an approach Samsung labels “XPU area reclamation.” AI accelerators are colliding with familiar scaling barriers, including slowing process gains and dies pushing against reticle and interposer limits. To free up room for more compute, Samsung plans to relocate non-compute blocks off the processor and onto the base die’s underused silicon.
The first target is the HBM Physical Interface (PHY), one of the largest blocks on the base die, which Samsung proposes to rework as part of that relocation. The base die’s move to a 4nm logic process is the foundation that makes this three-phase progression possible, shrinking interface circuitry while enabling the memory stack
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Image: tomshardware.com
