Hybrid bonding, the copper-to-copper joining method that eliminates solder microbumps in 3D chip stacks, is now in high-volume production for logic chips, even as its arrival in memory has been pushed back. The technique bonds two dies by first polishing them flat, then joining their copper pads and surrounding dielectric directly under heat and pressure, with no solder bump between them. Because there is no bump to collapse, connections can be packed far more tightly.
The density gains are substantial. AMD has cited roughly 15 times the interconnect density of conventional 2.5D microbump stacking. Figures presented at TSMC’s 2026 technology symposium placed face-to-face hybrid bonding at around 14,000 signals per square millimeter, compared with roughly 1,500 for face-to-back through-silicon-via stacking.
The leading chipmakers are already deep into deployment. TSMC has scaled its SoIC bond pitch from 9 microns to 6, with a roadmap targeting 4.5 microns by 2029. Intel began shipping Foveros Direct hybrid bonding in its Clearwater Forest server CPU during the first half of 2026. AMD has used the technology in volume since its first 3D V-Cache parts.
The HBM Delay No One Anticipated
Memory tells a different story. A JEDEC decision earlier this year to raise the HBM stack-height limit allows HBM4 to remain on the less sophisticated and less expensive microbump technology. That effectively defers hybrid bonding’s entry into high-bandwidth memory, which is now set to debut in HBM4E and HBM5 near the end of the decade.
Microbumps have historically operated at pitches around 40 microns, tightening toward 10 microns for the latest memory. Hybrid bonding begins where microbumps end and keeps scaling. The leading edge sits at 6 microns today, with 4.5- and 3-micron generations in development and sub-micron pitches demonstrated in research. Each step down multiplies the vertical connections between stacked dies, allowing a cache die or compute tile to behave as if it were part of the main chip rather than a separate component wired across a package.
Wafer-to-Wafer Versus Die-to-Wafer
The method splits into two approaches. Wafer-to-wafer bonding joins two full patterned wafers face-to-face and dices them afterward, enabling the tightest pitch and fastest production because alignment happens once at the wafer scale. Imec and EV Group demonstrated a 200-nanometer wafer-to-wafer pitch with post-bond overlay below 40 nanometers at ECTC in May. The trade-off is that both wafers must carry identically sized dies, and every die gets bonded, including defective ones, so a single bad die on either wafer ruins the pair.
Die-to-wafer bonding places individual, pre-tested dies onto a wafer, which is what chiplet and HBM stacks require. It permits known-good-die selection and the mixing of different die sizes and process nodes, but throughput suffers because each die is picked, aligned, and placed in sequence rather than in one wafer-scale step.
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Image: tomshardware.com
