Cerebras used Hot Chips 2026 to detail the next two generations of its wafer-scale accelerator roadmap, outlining plans to add stacked DRAM to a future wafer and to triple rack-scale performance with a new system design. The company’s SRAM-packed wafer-scale engines (WSEs) have found a niche in AI model serving, delivering low-latency, high-throughput inference that powers services such as OpenAI’s ChatGPT-5.6 Sol Ultrafast tier.
Building a large coherent processor on a single massive slice of silicon remains a distinctive achievement in the industry, but the approach comes with tradeoffs. AI memory requirements keep climbing as model sizes grow and as longer contexts fill large KV caches, which are unique to each inference session. Model memory can be spread across multiple sessions, but the pressure on available memory continues to increase.
Why Cerebras Is Turning to 3D Stacking
Traditional GPU vendors have eased these memory constraints by working with memory makers to stack HBM taller and to place more of it near the processor. That option is harder for a wafer-scale design, where the silicon area is already fully occupied by logic and memory. On such a chip, adding more of one resource means sacrificing area that could serve another purpose. With production expected to remain on 300mm wafers for the foreseeable future, Cerebras must find other ways to expand the on-chip resources feeding its processors.
The company’s answer arrives with the CS-6 system, which is two generations out on its roadmap. For the first time, Cerebras plans to attempt 3D stacking of DRAM on top of its logic and SRAM wafer. It says the move will preserve its inference performance lead while shrinking the area needed for the overall chip. That reduction in area could allow Cerebras to produce a greater number of WSEs, potentially easing a key supply constraint as it scales its business in a market defined by rising wafer demand.
CS-4 and the Nexus Rack Design
In the near term, Cerebras is raising the performance of its current platform with the CS-4 rack-scale system and its Nexus rack design. CS-4 packages three of the company’s refreshed WS-3T wafers into self-contained “backpacks” that combine power delivery, scale-up networking, and liquid cooling into a single pluggable module.
Because those modules are self-contained, Cerebras says future wafer-scale engines built on this architecture can be swapped in without replacing the entire rack. Chief system architect JP Fricker contrasted the design with the roughly 5,000 cables used to connect the Rubin NVL72 NVLink scale-up domain in competing racks, describing that cabling as a mess and pointing to the cleaner, less failure-prone approach enabled by on-die interconnects.
The Nexus architecture triples rack-scale performance for the CS-4 system, while stacked DRAM is slated to debut on the CS-6 wafer.
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Image: tomshardware.com
